1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device for performing a gear-down mode operation.
2. Description of the Related Art
A gear-down mode may be performed in a semiconductor memory device such as a double data rate 4 (DDR4) semiconductor memory device, which operates at a high speed.
The gear-mode represents an operation mode in which command and address signals are received on the basis of two periods (2tck) of an external clock signal for an operation stability of a semiconductor memory device.
For example, the DDR4 semiconductor memory device has a target operation speed of 3300 Mbps. It is difficult to satisfy a setup and hold margin between an external clock signal and the command and address signals during a high speed operation of the DDR4 semiconductor memory device and accomplish high mass production simultaneously. Thus, in the gear-down mode, the command and address signals are received on the basis of a second period (2 tck) instead of one period (1 tck) of an external clock signal, to obtain an operation stability of a semiconductor memory device. Through the gear-down mode, since a frequency of an internal clock signal is lowered to a half of a data clock signal and a pulse width is expanded, the setup and hold margin may be obtained until an operation speed of 1600 Mbps. That is, through the gear-down mode the operation stability of the semiconductor memory device which operates at a high speed, may be obtained.
A circuit which defines a timing among an internal clock signal, an external clock signal and the command and address signals must be included in a semiconductor memory device and a semiconductor system using the gear-down mode. However, since the external clock signal is a high frequency, it is difficult to coordinate the timing among the internal clock signal, the external clock signal and the command and address signals.